Directorate Of Technical Education

Directorate Of Technical Education has published Bids Are Invited For Lab Apparatus 1 15 -Verification And Interpretation Of Truth Table For And, Or, Not, Nand, Nor And Exor Gates. , To Design A Half Adder And Full Adder Using Gates And Verification Of Their Operation Construction Of A Full Adder Circuit Using Xor And Nand Gates And Verify Its Operation. , To Design A Half Subtractor And Full Subtractor Circuit With The Help Of Gates And Verify Their Operation , 4 Bit Adder Subtractor Circuit Using An Ic Verify The Operation. , Verification Of Truth Table Of Jk And Jk Master Slave Flip Flops. , Steps To Enter, Modify Data Program And To Execute A Program On 8085 Kit. , Writing And Execution Of Alp For Addition And Subtractions Of Two 8 Bit Numbers. , Writing And Execution Of Alp For Multiplication And Division Of Two 8 Bit Numbers. , Writing And Execution Of Alp For Arranging 10 Numbers In Ascending Descending Order. , Verify Of Truth Table For Decoder Ics , To Design A 4 Bit Siso, Sipo, Piso, Pipo Shift Register Using Jk D Flip Flop And Verification Of Their Operation , Design Decode Counter And Its Verification. , Design Analog To Digital And Digital To Analog Converters And Their Verification. , To Design A 4 Bit Binary Counter And Verify Its Truth Table. , To Determine The Output Of Rl, Rc, Rlc Series And Parallel Circuit. , Transient Response In R-L And R-C Network , Transient Response In R-L-C Series And Parallel Circuits Network , Determination Of Impedance Z And Admittance Y Parameters Of Two Port Network , Verification Of Kirchhoff Current And Voltage Laws Applied To Dc Circuit , To Construct An Rl And Rc Circuit And To Measure Impedance, Phase Angle Total Quantity : 40. Last date of submission for this tender is 2024-01-18. This is a Laboratory Equipment tender in CHAMOLI, Uttarakhand