Department Of Higher Education

Department Of Higher Education has published Bids Are invited for Software Licenses-UEF-VIVADO-ENETER-25 + UEF-MATSIM-ADDON-25 - Part1 - Vivado ML Enterprise Edition +Vitis Model Composer Plugin, University License- 25 License of Latest version , TUL PYNQ-Z2 board along with accessories(1M1-M000127DVA- Part 2) - ZYNQ XC7Z020-1CLG400C650MHz dual-core Cortex-A9 processor ,DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports, High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO , Low-bandwidth peripheral controller: SPI, UART, CAN, I2C, Programmable from JTAG, Quad-SPI flash, and microSD card, Programmable logic equivalent to Artix-7 FPGA, 13,300 logic slices, each with four 6-input LUTs and 8 flip-flops, 630 KB of fast block RAM, 4 clock management tiles, each with a phase locked loop (PLL) and mixed-mode clock manager (MMCM),220 DSP slices, On-chip analog-to-digital converter (XADC) , Arty A7-100: Artix-7 FPGA Development Board (410-319-1 - Part 3) - Xc7a35ticsg324-1L33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops), 1,800 Kbits of fast block RAM; o Five clock management tiles, each with a phaselocked loop (PLL), 90 DSP slices, Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash , Spartan-7 SP701 FPGA Evaluation Kit (EK-S7-SP701-G-Part4) - XCS7100102,400 logic cells in 16000 slices (each slice contains four 6-input LUTs and 8 flip-flops), 1,800 Kbits of fast block RAM; o Five clock management tiles, each with a phase locked loop (PLL), 160 DSP slices, I2C Programmable SYSCLK oscillator 33.33 MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash , Digilent 410-370 Development board (410-370-Part5 ) - XC7Z010-1CLG400C 35200 flip-flops, 80 DSP slices, 270 KB Block RAM, 17600 look up tablesXC7Z007S-1CLG400C, 28800 flip-flops, 66 DSP slices, 225 KB Block RAM, 14400 look up tables667MHz Cortex-A9 processor (dual core), On chi. Last date of submission for this tender is 2021-11-29. This is a Flip Flops tender in null, Delhi